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| copyright ? cirrus logic, inc. 2012 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs5490 two channel energy measurement ic features & description ? superior analog performance with ultra-low noise level & high snr ? energy measurement accuracy of 0.1% over a 4000:1 dynamic range ? two independent 24-bit, 4 th -order, delta-sigma modulators for voltage and current measurements ? configurable digital output for energy pulses, interrupt, zero-crossing, and energy direction ? supports shunt resistor, ct, and rogowski coil current sensors ? on-chip measurements/calculations: - active, reactive, and apparent power - rms voltage and current - power factor and line frequency - instantaneous voltage, current, and power ? overcurrent, voltage sag, and voltage swell detection ? ultra-fast on-chip digital calibration ? configurable no-load threshold for anti-creep ? internal register protection via checksum and write protection ? uart serial interface ? on-chip temperature sensor ? on-chip voltage reference (25ppm/c typ.) ? single 3.3 v power supply ? ultra-fine phase compensation ? low power consumption: <13 mw ? power supply configurations: - gnda = 0 v, vdda: +3.3 v ? low-cost 16-pin soic package description the cs5490 is a high-accuracy, two-channel, energy measure- ment analog front end. the cs5490 incorporates independent 4 th order delta-sigma an- alog-to-digital converters for bo th channels, reference circuitry, and the proven exl signal processing core to provide active, re- active, and apparent energy measurement. in addition, rms and power factor calculations are av ailable. calculations are output via a configurable energy pulse, or direct uart serial access to on-chip registers. instantaneous current, voltage, and power measurements are also available over the serial port. the two-wire uart minimizes the cost of isolation where required. a configurable digital output provides energy pulses, zero-cross- ing, energy direction, or inte rrupt functions. interrupts can be generated for a variety of condi tions including voltage sag or swell, overcurrent, and more. on-chip register integrity is assured via checksum and write protection. t he cs5490 is designed to in- terface to a variety of voltage and current sensors, including shunt resistors, current transformers, and rogowski coils. on-chip functionality makes digital calibration simple and ultra fast to minimize the time required at the end of the customer pro- duction line. performance across temperature is ensured with an on-chip voltage reference with low drift. a single 3.3v power sup- ply is required, and power cons umption is low at <13mw. to minimize space requirements, the cs5490 is offered in a low-cost 16-pin soic package. ordering in formation see page 56 . vdda gnda reset calculation temperature sensor vref+ voltage reference vddd vref- system clock cs5490 mode clock generator xin xout tx rx uart serial interface 4th order ?? modulator digital filter hpf option iin + iin- pga digital filter hpf option 10x vin+ vin- 4th order ?? modulator do configurable digital output jun?12 ds982f2
cs5490 2 ds982f2 table of contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 analog pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1.1 voltage input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1.2 current input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1.3 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2 digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.2 digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.3 uart serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.3.1 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.4 mode pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. characteristics & specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. signal flow description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.1 analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 decimation filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 iir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 dc offset & gain correcti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.6 high-pass & phase matching filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 digital integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 low-rate calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8.1 fixed number of sa mples averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8.2 line-cycle synchronized averagi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.8.3 rms current & voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.4 active power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.8.5 reactive power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.6 apparent power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.7 peak voltage & curr ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.8 power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.9 average active power offs et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.10 average reactive po wer offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 zero-crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 line frequency measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 energy pulse generati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.1 pulse rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.2 pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 voltage sag, voltage swe ll, and overcurrent detect ion . . . . . . . . . . . . . . . . . . . . .21 5.7 phase sequence detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 cs5490 ds982f2 3 5.9 anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10.1 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10.2 register checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. host commands and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 host commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.1 memory access commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.1.1 page select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.1.2 register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.1.3 register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.3 checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.4 serial time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 hardware registers summ ary (page 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 software registers summary (page 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 software registers summary (page 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.5 software registers summary (page 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.6 register descript ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. system calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 calibration in general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1 offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1.1 dc offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1.2 ac offset calibrat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.2 gain calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.1.3 calibration order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3 temperature sensor calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3.1 temperature offset and gain calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8. basic application circ uits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 11. environmental, manufac turing, & handling informati on . . . . . . . . . . . . . . . . . . . . . . . 56 12. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 cs5490 4 ds982f2 list of figures figure 1. oscillator connections............................................................................................... .... 7 figure 2. uart serial frame format ........................................................................................... 7 figure 3. active energy load performance.................................................................................. 8 figure 4. reactive energy load performance.............................................................................. 9 figure 5. irms load performance ............................................................................................... 9 figure 6. signal flow for v, i, p, and q measurements ............................................................. 15 figure 7. low-rate calculations ................................................................................................ .. 16 figure 8. power-on reset timing ............................................................................................... 1 8 figure 9. zero-crossing level and zero-crossing output on do ................................................ 19 figure 10. energy pulse generation and digital output control ................................................ 20 figure 11. sag, swell, & overcurrent detect.............................................................................. 21 figure 12. phase sequence a, b, c fo r rising edge transition ................................................ 22 figure 13. phase sequence c, b, a for rising edge transition ................................................ 23 figure 14. byte sequence for page select................................................................................. 24 figure 15. byte sequence for register read ............................................................................ 24 figure 16. byte sequence for register write ............................................................................. 24 figure 17. byte sequence for instructions.................................................................................. 24 figure 18. byte sequence for checksum ................................................................................... 25 figure 19. calibration data flow ............................................................................................... .51 figure 20. t register vs. force temp ........................................................................................ 53 figure 21. typical connection diagram (single-phase, two-wire, power meter) ...................... 54 list of tables table 1. por thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2. command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3. instruction format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cs5490 ds982f2 5 1. overview the cs5490 is a cmos power measurement integrated circuit that uses two ?? analog-to-digital converters to measure line voltage and current. the cs5490 calculates active, reactive, and apparent power as well as rms voltage and current and peak voltage and current. it handles other system-related functions, such as energy pulse generation, volt age sag and swell, overcurrent and zero-crossing detection, and line frequency measurement. a separate analog-to-digital converter is used for on-chip temperature measurement. the cs5490 is optimized to interface to current tr ansformers, shunt resistors, or rogowski coils for current measurement, and to resistive dividers or voltage transformers for voltage measurement. two full-scale ranges are provided on the current input to accommodate different types of current sensors. the cs5490?s two differential inputs have a common-m ode input range from analog ground (gnda) to the positive analog supply (vdda). an on-chip voltage reference (typically 2.4 volts) is generated and provided at analog output, vref. the digital output (do) provides a variety of output signals and, depending on the mode selected, provides energy pulses, zero-crossings, or other choices. the cs5490 includes a uart serial host interfac e to an external microcontroller. the uart signals include serial data input (rx) and serial data output (tx). cs5490 6 ds982f2 2. pin description 2.1 analog pins the cs5490 has two differential inputs, one for voltage (vin ? ) and one for current ?? iin ? ). the cs5490 also has two voltage reference pins (vref ? ) between which a 0.1 bypass capacitor must be placed. 2.1.1 voltage input the output of the line voltage resistive divider or transformer is connected to the vin ? input of the cs5490. the voltage channel is equipped with a 10x, fixed-gain amplifier. the full-scale signal level that can be applied to the voltage channel is 250 mv. if the input signal is a sine wave, the maximum rms voltage is 250mvp / ? 2 ? 176.78mv rms , which is approximately 70.7% of maximum peak voltage. 2.1.2 current input the output of the current-s ensing shunt resistor or transformer is connected to the iin ? input pins of the cs5490. to accommodate different current-sensing elements, the current channel incorporates a programmable gain amplifier (pga) with two selectable input gains, as described in the config0 register description 6.6.1 configuration 0 (config0) ? page 0, address 0 on page 31. there is a 10x gain setting and a 50x gain setting. the full- scale signal level for the current channel is 50mv and 250mv for 50x and 10x gain settings, respectively. if the input signal is a sine wave, the maximum rms voltage is 35.35 mv rms or 176.78mv rms , which is approximately 70.7% of maximum peak voltage. clock generator crystal in crystal out 2,1 xin, xout ? connect to an external quartz crystal. alternatively, an exte rnal clock can be supplied to the xin pin to provi de the system clock for the device. control pins and serial data i/o digital output 12 do ? configurable digital output for energy pulses, interrupt, energy direction, and zero-crossings. reset 3 reset ? an active-low schmitt-trigger input used to reset the chip. serial interface 13,14 tx, rx ? uart serial data output/input. operating mode select 15 mode ? connect to vdda for proper operation. analog inputs/outputs voltage input 6,7 vin+, vin- ? differential analog input for the voltage channel. current input 5,4 iin+, iin- ? differential analog input for the current channel. voltage reference input 9,8 vref+, vref- ? the voltage reference output and return. power supply connections internal digital supply 16 vddd ? decoupling pin for the internal digital supply. positive analog supply 11 vdda ? the positive analog supply. analog ground 10 gnda ? analog ground. 1 7 6 5 4 3 2 8 16 10 11 12 13 14 15 9 xout vref- vin- vin+ iin+ iin- reset xin vddd vref+ gnda vdda do tx rx mode cs5490 ds982f2 7 2.1.3 voltage reference the cs5490 generates a stable voltage reference of 2.4v between the vref ? pins. the reference system also requires a filter capacitor of at least 0.1f between the vref ? pins. the reference system is capable of providing a reference for the cs5490 but has limited ability to drive external circuitry. it is strongly recommended that nothing other than the required filter capacitor is connected to the vref ? pins. 2.1.4 crystal oscillator an external, 4.096mhz quartz crystal can be connected to the xin and xout pins as shown in figure 1 . to re- duce system cost, each pin is supplied with an on-chip load capacitor. alternatively, an external clock source can be connected to the xin pin. 2.2 digital pins 2.2.1 reset input the active-low reset pin, when asserted for longer than 120s, will halt all cs5490 operations and reset internal hardware registers and states. when de-asserted, an initialization sequence begins, setting the default register values. to prevent erroneous, noise-induced resets to the part, an external pull-up resistor and a decoupling capacitor are necessary on the reset pin. 2.2.2 digital output the cs5490 provides a configurable digital output (do). it can be configured to output energy pulses, interrupt, zero-crossings, or energy directions. refer to the description of the config1 register in section 6.6 register descriptions on page 31 for more details. 2.2.3 uart serial interface the cs5490 provides two pins, rx and tx, for communication between a host microcontroller and the cs5490. 2.2.3.1 uart the cs5490 provides a two-wire, asynchronous, full-duplex uart port. the cs5490 uart operates in 8-bit mode, which transmits a total of 10 bits per byte. data is transmitted and rece ived lsb first, with one start bit, eight data bits, and one stop bit. figure 2. uart se rial frame format the baud rate is defined in the serialctrl register. after chip reset, the default baud rate is 600, if mclk is 4.096mhz. the baud rate is based on the contents of bits br[15:0] in the serialctrl register and is calculated as follows: br[15:0] = baud rate x (524288/mclk) or baud rate = br[15:0] / (524288/mclk) the maximum baud rate is 512k if mclk is 4.096mhz. the uart has two signals: tx and rx. tx is the serial data output from the cs5490; rx is the serial data input to the cs5490. 2.2.4 mode pin the mode pin must be tied to vdda for normal operation. the mode pin is used primarily for factory test procedures. xin xout c1 = 22pf c2 = 22pf figure 1. oscillator connections 0 1 2 7 idle stop 3 4 5 6 start data idle cs5490 8 ds982f2 3. characteristics & specifications recommended operating conditions power measuremen t characteristics notes: 1. specifications guaranteed by design and characterization. 2. active energy is tested with power factor pf = 1.0. reactive energy is tested with sin( ? ) = 1.0. energy error measured at system level using single energy pulse. where: 1) one energy pulse = 0.5wh or 0.5varh; 2) vdda = +3.3v, t a = 25c, mclk = 4.096mhz; 3) system is calibrated. 3. calculated using register values; n 4000. 4. i rms error calculated using register values. 1) vdda = +3.3v; t a = 25c; mclk = 4.096mhz; 2) ac offset calibration applied. typical load performance ? energy error measured at system le vel using single energy pulse; where 1 energy pulse = 0.5wh or 0.5varh. ?i rms error calculated using register values ? vdda = +3.3v; t a = 25c; mclk = 4.096mhz parameter symbol min typ max unit positive analog power supply vdda 3.0 3.3 3.6 v specified temperature range t a -40 - +85 c parameter symbol min typ max unit active energy all gain ranges (note 1 & 2) current channel input signal dynamic range 4000:1 p avg -0.1- % reactive energy all gain ranges (note 1 & 2) current channel input signal dynamic range 4000:1 q avg -0.1- % apparent power all gain ranges (note 1 & 3) current channel input signal dynamic range 1000:1 s-0.1-% current rms all gain ranges (note 1, 3, & 4) current channel input signal dynamic range 1000:1 i rms -0.1- % voltage rms (note 1 & 3) voltage channel input signal dynamic range 20:1 v rms -0.1- % power factor all gain ranges (note 1 & 3) current channel input signal dynamic range 1000:1 pf - 0.1 - % -1 -0.5 0 0.5 1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 percent error (%) current dynamic range (x : 1 ) lagging pf = 0.5 leading pf = 0.5 pf = 1 figure 3. active en ergy load performance cs5490 ds982f2 9 -1 -0.5 0 0.5 1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 percent error (%) current dynamic range (x : 1 ) lagging sin( n ) = 0.5 leading sin( n ) = 0.5 sin( n ) = 1 figre 4. reaie energ load perorane -1 -0.5 0 0.5 1 0 500 1000 1500 percent error (%) current dynamic range (x : 1) irms error i rms error figre 5. i rms load perorane cs5490 10 ds982f2 analog characteristics ? min/max characteristics and specif ications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications ar e measured at nominal supply voltages and t a = 25c. ? vdda = +3.3v 10%; gnda = 0v. all voltages with respect to 0v. ? mclk = 4.096mhz. parameter symbol min typ max unit analog inputs (current channels) common mode rejection (dc, 50, 60hz) cmrr 80 - - db common mode+signal -0.25 - vdda v differential full-scale input range (gain = 10) [(iin+) ? (iin-)] (gain = 50) iin - - 250 50 - - mv p mv p total harmonic distortion (gain = 50) thd 90 100 - db signal-to-noise ratio (snr) (gain = 10) (gain = 50) snr - - 80 80 - - db db crosstalk from voltage inputs at full scale (50, 60hz) --115-db crosstalk from current input at full scale (50, 60hz) --115-db input capacitance ic - 27 - pf effective input impedance eii 30 - - k ? offset drift (without the high-pass filter) od - 4.0 - v/c noise (referred to input) (gain = 10) (gain = 50) n i - - 9 2.2 - - v rms v rms power supply rejection ratio (60hz) (note 7) (gain = 10) (gain = 50) psrr 60 68 65 75 - - db db analog inputs (voltage channels) common mode rejection (dc, 50, 60hz) cmrr 80 - - db common mode+signal -0.25 - vdda v differential full-scale input range [(vin+) ? (vin-)] vin - 250 - mv p total harmonic distortion thd 80 88 - db signal-to-noise ratio (snr) snr - 73 - db crosstalk from current inputs at full scale (50, 60hz) --115-db input capacitance ic - 2.0 - pf effective input impedance eii 2 - - m ? noise (referred to input) n v -40-v rms offset drift (without the high-pass filter) od - 16.0 - v/c power supply rejection ratio (60hz) (note 7) (gain = 10) psrr 60 65 - db temperature temperature accuracy (note 6) t-5-c cs5490 ds982f2 11 notes: 5. all outputs unloaded. all inputs cmos level. 6. temperature accuracy measured after calibration is performed. 7. measurement method for psrr: vdda = +3.3v, a 150mv (zero-to-p eak) (60hz) sinewave is imposed onto the +3.3v dc supply voltage at the vdda pin. the ?+? and ?-? input pins of both i nput channels are shorted to gnda. the cs5490 is then commanded to continuous conversion acquisi tion mode, and digital output data is collected for the channel under test. the (zero-to-peak) value of the digital sinusoidal output signal is determined, and this val ue is converted into the (zero- to-peak) value of the sinusoi dal voltage (measured in mv) that would need to be applied at the channel?s inputs, in order to cause the same digital sinusoidal output. this voltage is then defined as v eq psrr is (in db) : voltage reference notes: 8. it is strongly recommended that no connection other than the required filter capacitor be made to vref. 9. the voltage at vref is measured across the temperature range. from these measurements the fo llowing formula is used to calculate the vref temperature coefficient: 10. specified at maximum recommended output of 1a sourcing. vref is a very sensitive signal, the output of the vref circuit has a very high output impedance so that the 0.1f reference capaci tor provides attenuation even to low frequency noise, such as 50hz noise on the vref output. as such vref intended fo r the cs5490 only and should not be connected to any external circuitry. the output impedance is sufficient ly high that standard digital multi-meters can significantly load this voltage. th e accuracy of the metrology ic can not be guaranteed when a mult imeter or any component other than the 0.1f capacitor is attached to vref. if it is desired to measure vref for any reason other than a very course indicator of vref functionality, cir rus recommends a very high input impedance multimeter such as the keithley model 2000 digital multimeter be used, but still cannot guarantee the accuracy of the metrology with this meter connected to vref. power supplies power supply currents (active state) i a+ (vdda = +3.3v) psca - 3.9 - ma power consumption (note 5) active state (vdda = +3.3v) stand-by state pc - - 12.9 4.5 - - mw mw parameter symbol min typ max unit reference (note 8) output voltage vref +2.3 +2.4 +2.5 v temperature coefficient (note 9) tc vref -25-ppm/c load regulation (note 10) ? v r -30-mv parameter symbol min typ max unit psrr 20 150 v eq ---------- - log ? = tc vref vref max vref min ? vref avg ------------------------------------------------------------ ?? ?? 1 t a max t a min ? --------------------------------------------- - ?? ?? 1.0 10 6 ? ?? = cs5490 12 ds982f2 digital characteristics ? min / max characteristics and specif ications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications ar e measured at nominal supply voltages and t a = 25c. ? vdda = +3.3v 10%; gnda = 0v. all voltages with respect to 0v. ? mclk = 4.096mhz. notes: 11. all measurements perfo rmed under static conditions. 12. xout pin used for crystal only. typical drive current<1ma. parameter symbol min typ max unit master clock characteristics xin clock frequency internal gate oscillator mclk 2.5 4.096 5 mhz xin clock duty cycle 40 - 60 % filter characteristics phase compensation range (60hz, owr = 4000hz) -10.79 - +10.79 input sampling rate - mclk/8 - hz digital filter output word rate (both channels) owr - mclk/1024 - hz high-pass filter corner frequency -3db -2.0-hz input/output characteristics high-level input voltage (all pins) v ih 0.6(vdda) - - v low-level input voltage (all pins) v il --0.6v high-level output voltage do, i out =+10ma (note 12) i out =+5ma v oh vdda-0.3 vdda-0.3 - - - - v v low-level output voltage do, i out =-12ma (note 12) all other outputs, i out =-5ma v ol - - - - 0.5 0.5 v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf cs5490 ds982f2 13 switching characteristics ? min / max characteristics and specif ications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications ar e measured at nominal supply voltages and t a = 25c. ? vdda = +3.3v 10%; gnda = 0v. all voltages with respect to 0v. ? logic levels: logic 0 = 0v, logic 1 = vdda. notes: 13. specified using 10% and 90% points on wa veform of interest. output loaded with 50pf. 14. oscillator start-up time varies with cryst al parameters. this specification does not apply when using an external clock sour ce. parameter symbol min typ max unit rise times do (note 13) any digital output except do t rise - - - 50 1.0 - s ns fall times do (note 13) any digital output except do t fall - - - 50 1.0 - s ns start-up oscillator st art-up time xtal = 4.096 mhz (note 14) t ost -60-ms cs5490 14 ds982f2 absolute maximum ratings notes: 15. vdda and gnda must satisfy [(vdda) ? (gnda)] ? + 4.0v. 16. applies to all pins, includi ng continuous overvoltage conditions at the analog input pins. 17. transient current of up to 100 ma will not cause scr latch-up. 18. applies to all pins, except vref . 19. total power dissipation, including all input currents and output currents. 20. applies to all pins. warning: operation at or beyond these limits may re sult in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit dc power supplies (note 15) vdda -0.3 - +4.0 v input current (notes 16 and 17) i in -- 10ma input current for power supplies - - - 50 - output current (note 18) i out -- 100ma power dissipation (note 19) p d -- 500mw input voltage (note 20) v in - 0.3 - (vdda) + 0.3 v junction-to-ambient thermal impedance 2 layer board 4 layer board ? ja - - 140 70 - - c/w c/w ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c cs5490 ds982f2 15 4. signal flow description the signal flow for voltage, current measurement, and the other calculations is shown in figure 6 . the signal flow consists of a current and a voltage channel. the current and voltage channels have differential input pins. 4.1 analog-to-digital converters both input channels use fourth-order delta-sigma modulators to convert the analog inputs to single-bit digital data streams. the converters sample at a rate of mclk/8. this high sampling provides a wide dynamic range and simplifies anti- alias filter design. 4.2 decimation filters the single-bit modulator output data is widened to 24 bits and down sampled to mclk/1024 with low-pass decimation filters. these decimation filters are third-order sinc filters. the filter outputs pass through an iir "anti-sinc" filter. 4.3 iir filter the iir filter is used to compensate for the amplitude roll-off of the decimation filters. the droop-correction filter flattens the magnitu de response of the channel out to the nyquist frequency, th us allowing for accurate measurements of up to 2khz (mclk = 4.096mhz). by default, the iir filters are enabled. the iir filters can be bypassed by setting the iir_off bit in the config2 register. 4.4 phase compensation phase compensation changes the phase of voltage relative to current by adding a delay in the decimation filters. the amount of phase shift is set by the pc register bits cpcc[1:0] and fpcc[8:0] for the current channel. for the voltage channel, only bits cpcc[1:0] affect the delay. fine phase compensation control bits, fpcc[8:0], provide up to 1/owr delay in the current channel. coarse phase compensation control bits, cpcc[1:0], provide an additional 1/owr delay in the current channel or up to 2/owr delay in the voltage channel. negative delay in the voltage channel can be implemented by setting longer delay in the current channel than the voltage channel. for a owr of 4000hz, the delay range is 500s, a phase shift of 8.99 at 50hz and 10.79 at 60hz. the step size is 0.008789 at 50hz and 0.010547 at 60hz. for more information about phase compensation, see section 7.2 phase compensation on page 52. 4.5 dc offset & gain correction the system and cs5490 inherently have component tolerances, gain, and offset errors, which can be removed using the gain and offset registers. each measurement channel has its own set of gain and offset registers. for every instantaneous voltage and current sample, the offset and gain values are used to correct dc offset and gain errors in the channel (see section 7. system calibration on page 51 for more details). mux vin sinc 3 iin sinc 3 pga hpf 4 th order ? modulator 4 th order ? modulator x10 delay ctrl 2 ? mux pmf hpf pmf iir iir phase shift config 2 epsilon delay ctrl int registers q v p i sys gain ... ... iflt[1:0] vflt[1:0] v dcoff i dcoff i gain v gain pc ... ... fpcc[8:0] cpcc[1:0] ... figure 6. signal flow for v, i, p, and q measurements cs5490 16 ds982f2 4.6 high-pass & phase matching filters optional high-pass filters (hpf in figure 6 ) remove any dc component from the selected signal paths. each power calculation contains a current and voltage channel. if an hpf is enabled in only one channel, a phase-matching filter (pmf) should be applied to the other channel to match the phase response of the hpf. for ac power measurement, high-pass filters should be enabled on the voltage and current channels. for information about how to enable and disable the hpf or pmf on each channel, refer to config2 register descriptions in section 6.6 register descriptions on page 31. 4.7 digital integrators optional digital integrators (int in figure 6 ) are implemented on the current channel to compensate for the 90 phase shift and 20db/decade gain generated by the rogowski coil curr ent sensor. when a rogowski coil is used as the current sensor, the integrator (int) should be enabled on that current channel. for information about how to enable and disable the int on the current channel, refer to config2 register descriptions in section 6.6 register descriptions on page 31. 4.8 low-rate calculations all the rms and power result s come from low-rate cal- culations by averaging the output word rate (owr) in- stantaneous values over n samples, where n is the value stored in the samplecount register. the low-rate interval or averaging period is n divided by owr (4000hz if mclk = 4.096mhz). the cs5490 provides two averaging modes for low- rate calculations: fixed number of sample averaging mode and line-cycle synchronized averaging mode . by default, the cs5490 averages with the fixed number of samples averaging mode. by setting the avg_mode bit in the config2 reg- ister, the cs5490 will use th e line-cycle synchronized averaging mode. 4.8.1 fixed number of samples averaging n is the preset value in the samplecount register and should not be set less th an 100. by default, the samplecount register is 4000. with mclk = 4.096 mhz, the averaging period is fixed at n/4000 = 1 second, regardless of the line frequency. 4.8.2 line-cycle synchronized averaging when operating in line-cycle synchronized averaging mode, and when line frequency measurement is enabled (see section 5.4 line frequency measurement on page 19), the cs5490 uses the voltage (v) channel zero crossings and measured line frequency to automatically adjust n such that the averaging period will be equal to the number of half line-cycles in the cyclecount register. for example, if the line frequency is 51hz, and the cyclecount register is set to 100, n will be 4000 ? (100/2)/51 = 3921 during continuous conversion. n is self-adjusted a ccording to the line frequency, therefore the averaging period is always close to the whole number of half line-cycles, and the low-rate calculation resu lts will minimize ripple and maximize resolution, especially when the line frequency varies. before starting a low-rate conversion in the line-cycle synchronized averaging mode, the n n ? n n ? n n ? n n ? registers mux ... ... apcm config 2 v i p q i acoff s ? ? pf x i rms v rms q avg p avg - + q off ? + + p off ? + + x x + + inverse figure 7. low-rate calculations cs5490 ds982f2 17 samplecount register should not be changed from its default value of 4000, and bit afc of the config2 register must be set. during continuous conversion, the host processor should not change the samplecount register. 4.8.3 rms current & voltage the root mean square ( rms in figure 7 ) calculations are performed on n instantaneous voltage and current samples using equation 1: 4.8.4 active power the instantaneous voltage and current samples are multiplied to obtain th e instantaneous power ( p ) (see figure 6 ). the product is then averaged over n samples to compute active power ( p avg ). 4.8.5 reactive power instantaneous reactive power ( q ) is the sample rate result obtained by multiply ing instantaneous current ( i ) by instantaneous quadrature voltage ( q ). these values are created by phase shifting instantaneous voltage ( v ) 90 using first-order integrators (see figure 6 ). the gain of these integrators is inversely related to line frequency, so their gain is corrected by the epsilon register, which is based on line frequency. reactive power ( q avg ) is generated by integrating the instantaneous quadrature power over n samples. 4.8.6 apparent power by default, the cs5490 calculates the apparent power ( s ) as the product of rms voltage and current. see equation 2: the cs5490 also provides an alternate apparent power calculation method. the alternate apparent power method uses real power ( p avg ) and reactive power ( q avg ) to calculate apparent power. see equation 3. the apcm bit in the config2 register controls which method is used for apparent power calculation. 4.8.7 peak voltage & current peak current ( i peak ) and peak voltage ( v peak ) are cal- culated over n samples and recorded in the corre- sponding channel peak register documented in the register map. this peak value is updated every n samples. 4.8.8 power factor power factor ( pf ) is active power divided by apparent power, as shown below. the sign of the power factor is determined by the active power. see equation 4. 4.9 average active power offset the average active power offset register, p off , can be used to offset erroneous power sources resident in the system not originating from the power line. residual power offsets are usually caused by crosstalk into the current channel from the voltage channel, or from ripple on the meter?s or chip?s power supply, or from inductance from a nearby transformer. these offsets can be either positive or negative, indicating crosstalk coupling either in phase or out of phase with the applied voltage input. the power offset register can compensate for either condition. to use this feature, measure the average power at no load and take the measured result (from the p avg register), invert (negate) the value, and write it to the associated power offset register, p off . 4.10 average react ive power offset the average reactive power offset register, q off , can be used to offset erroneous power sources resident in the system not originating from the power line. residual reactive power offsets are usually caused by crosstalk into the current channel from the voltage channel, or from ripple on the meter?s or chip?s power supply, or from inductance from a nearby transformer. these offsets can be either positive or negative, depending on the phase angle between the crosstalk coupling and the applied voltage. the reactive power offset register can compensate for either condition. to use this feature, measure the average reactive power at no load. take the measured result from the q avg register, invert (negate) the value and write it to the reactive power offset register, q off . i rms i n 2 n0 = n1 ? ? n ------------------- - = v rms v n 2 n0 = n1 ? ? n ---------------------- = [eq. 1] sv rms i rms ? = [eq. 2] sq avg 2 p avg 2 + = [eq. 3] pf p active s ---------------------- = [eq. 4] cs5490 18 ds982f2 5. functional description 5.1 power-on reset (por) the cs5490 has an internal power supply supervisor circuit that monitors the vdda and vddd power supplies and provides the master reset to the chip. if any of these voltages are in the reset range, the master reset is triggered. both the analog and the digital supply have their own por circuit. during power-up, both supplies have to be above the rising threshold for the master reset to be de-asserted. each por is divided into 2 blocks: rough and fine. rough por triggers the fine por. rough por depends only on the supply voltage. the trip point for the fine por is dependent on bandgap voltage for precise control. the por circuit also acts as a brownout detect. the fine por detects supply drops and asserts the master reset. the rough and fine pors have hysteresis in their rise and fall thresholds which prevents the reset signal from chattering. the following plot shows the por outputs for each of the power supplies. the por_fine_vdda and por_fine_vddd signals are and-ed to form the actual power-on reset signal to the digital circuity. the digital circuitry, in turn, holds the master reset signal for 130ms and then de-asserts the master reset. figure 8. power-on reset timing table 1. por thresholds 5.2 power saving modes power saving modes for cs5490 are accessed through the host instruction commands (see 6.1 host commands on page 24). ? standby: powers down all the adcs, rough buffer, and the temperature sensor. standby mode disables the system time calculations. use the wake-up command to come out of standby mode. ? wake-up: clears the adc power-down bits and starts the system time calculations. after any of these commands are completed, the drdy bit is set in the status0 register. 5.3 zero-crossing detection zero-crossing detection logic is implemented in cs5490. a low-pass filter can be enabled by setting zx_lpf bit in register config2 . the low-pass filter has a cut-off frequency of 80hz. it is used to eliminate any harmonics and to help the zero-crossing detection on the 50hz or 60hz fundamental component. the zero-crossing level register s are used to set the minimum threshold over which the channel peak has to exceed in order for the zero-crossing detection logic to function. there are two separate zero-crossing level registers: vzx level is the threshold for the voltage channels, and izx level is the threshold for the current channels. vdda por_rough_vdda por_fine_vdda vddd por_rough_vddd por_fine_vddd por_fine_vdda por_fine_vddd master reset 130ms v th1 v th2 v th5 v th6 v th3 v th4 v th7 v th8 typical por threshold rising falling vdda rough v th1 =2.34v v th6 =2.06v fine v th2 =2.77v v th5 =2.59v vddd rough v th3 =1.20v v th8 =1.06v fine v th4 =1.51v v th7 =1.42v cs5490 ds982f2 19 5.4 line frequency measurement if the automatic frequency calculation (afc) bit in the config2 register is set, the line frequency measurement on the voltage channel w ill be enabled. the line frequency measurement is based on a number of voltage channel zero crossings. this number is 100 by default and configurable through the zx num register (see section 6.6.56 on page 50). the epsilon register will be updated automatica lly with the line frequency information. the frequency update (fup) bit in the status0 interrupt status register is set when the frequency calculation is completed. when the line frequency is 50hz and the zx num register is 100, the epsilon register is updated every one second with a resolution of less than 0.1%. a larger zero-crossing number in the zx num register will increase line frequency measurement resolution and period. note that the cs5490 line frequency measurement function does not support the line frequency out of the range of 40hz to 75hz. the epsilon register is also used to set the gain of the 90 phase shift filter used in the quadrature power calculation. the value in the epsilon register is the ratio of the line frequency to the output word rate (owr). for 50hz line frequency and 4000hz owr, epsilon is 50/4000 (0.0125) (the default). for 60hz line frequency, it is 60/4000 (0.015). 5.5 energy pulse generation the cs5490 provides an independent energy pulse generation (epg) block in order to output active, reactive, and apparent energy pulses on the digital output pin (do). the energy pulse frequency is proportional to the magnitude of the power. the energy pulse output is commonly used as the test output of a power meter. the host microcontroller can also use the energy pulses to easily accumulate the energy. refer to figure 10 . v zx level izx level if |v peak | > vzx level , then voltage zero-crossing detection is enabled. if |i peak | > izx level , then current zero-crossing detection is enabled. zero-crossing output on dox pin pulse width = 250s v( t ), i( t ) do t t if |v peak | ? vzx level , then voltage zero-crossing detection is disable d. if |i peak | ? izx level , then current zero-crossing detection is disabled. figure 9. zero-crossing level and zero-crossing output on do cs5490 20 ds982f2 after reset, the energy pulse generation block is disabled (domode[3:0] = hi -z). to output a desired energy pulse to a do pin, it is necessary to follow the steps below: 1. write to register pulsewidth (page 0, address 8) to select the energy pulse width and pulse frequency range. 2. write to register pulserate (page 18, address 28) to select the energy pulse rate. 3. write to register pulsectrl (page 0, address 9) to select the input to the energy pulse generation block. 4. write ?1? to bit epg_on of register config1 (page 0, address 1) to enable the energy pulse generation block. 5. wait at least 0.1s. 6. write bits domode[3:0] of register config1 to select do to output pulses from the energy pulse generation block. 7. send dsp instruction (0xd5) to begin continuous conversion. 5.5.1 pulse rate before configuring the pulserate register, the full-scale pulse rate needs to be calculated, and the frequency range needs to be specified through freq_rng[3:0] bits in the pulsewidth register. for example, if a meter has the meter constant of 1000imp/kwh, a maximum voltage (u max ) of 240v, and a maximum current (i max ) of 100a, the maximum pulse rate is: [1000x(240x100/1000)]/3600 = 6.6667hz. assume the meter is calibrated with u max and i max , and the scale register contains the default value of 0.6. after gain calibration, the power register value will be 0.36, which represents 240 x 100 = 24kw or 6.6667hz pulse output rate. the full-scale pulse rate is: f out = 6.6667/0.36 = 18.5185hz. refer to section 6.6.6 pulse output width (pulsewidth) ? page 0, address 8 on page 35. the freq_rng[3:0] bits should be set to b[0110]. p sum sign q sum sign p sign q sign reserved v crossing i crossing do_od ( config1 ) ( pulsectrl ) epgin[3:0] domode[3:0] ( config1 ) do hi-z interrupt p sum q sum s sum p avg q avg s pulse rate epg_on ( config1 ) mclk ( pulsewidth ) pw[7:0] ( pulsewidth ) freq_rng[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 energy pulse generation (epg) 4 4 8 4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 digital output mux (do) reserved reserved reserved reserved reserved reserved reserved reserved reserved figure 10. energy pu lse generation and digital output control cs5490 ds982f2 21 the cs5490 pulse generation block behaves as follows: ? the pulse rate generated by full-scale (1.0 decimal) power register is f out =( pulserate x 2000)/2 freq_rng ?the pulserate register value is pulserate = (f out x2 freq_rng )/2000 = (18.5186 x 64)/2000 = 0.5925952 = 0x4bda29 5.5.2 pulse width the pulsewidth register defines the active-low time of each energy pulse: active-low = 250s + ( pulsewidth /64000). by default, the pulsewidth register value is 1, and the active-low time of each energy pulse is 265.6s. note that the pulse width should never exceed the pulse period. 5.6 voltage sag, voltage swell, and overcurrent detection voltage sag detection is used to determine when the voltage falls below a predete rmined level for a specified interval of time (duration). voltage swell and overcurrent detection determine when the voltage or current rises above a predetermined level for the duration. the duration is set by the value in the vsag dur , vswell dur , and iover dur registers. setting any of these to zero (default) disabl es the detect feature for the given channel. the value is in output word rate (owr) samples. the predetermined level is set by the values in the vsag level , vswell level , and iover level registers. for each enabled input channel, the measured value is rectified and compared to the associated level register . over the duration window, the number of samples above and below the level are counted. if the number of samples below the level exceeds the number of samples above, a status0 register bit vsag is set, indicating a sag condition. if the number of samples above the level exceeds the number of samples below, a status0 register bit vswell or iover is set, indicating a swell or overcurrent condition (see figure 11 ). level duration figure 11. sag, swell, & overcurrent detect cs5490 22 ds982f2 5.7 phase sequence detection polyphase meters using multiple cs5490 devices may be configured to sense the succession of voltage zero-crossings and determine which phase order is in service. the phase sequence detection within cs5490 involves counting the number of owr samples from a starting point to the next voltage zero-crossing rising edge or falling for each pha se. by comparing the count for each phase, the phase sequence can be easily determined: the smallest coun t is first, and the largest count is last. the phase sequence detection and control ( psdc ) register provides the coun t control, zero-crossing direction and count results. writing '0' to bit done and '10110' to bits code[4:0] of the psdc register followed by a falling edge on the rx pin will initiate the phase sequence detection circuit. the rx pin must be held low for a minimum of 500ns. when the device is in uart mode, it is recommended that a 0xff command be written to all parts to start the phase sequence detection. multiple cs549 0 devices in a polyphase meter must receive the re gister writing and the rx falling edge at the same time so that all cs5490 devices starts to count simultaneously. bit dir of psdc register specifies the direction of the next zero crossing at which the count stops. if bit dir is '0', the count stops at the next negative-to-positive zero crossing. if bit dir is '1', the count stops at the next positive-to-negative zero crossing. when the count stops, the done bit will be set by the cs5490, and then the count result of each phase may be read from bits pscnt[6:0] of the psdc register. if the pscnt[6:0] bits are equal to 0x00, 0x7f or greater than 0x64 (for 50hz) or 0x50 (for 60hz), then a measurement error has occurred, and the measurement results should be disregarded. this could happen when the voltage input signal amplitude is lower than the amplitude specified in the vzx level register. to determine the phase order, the pscnt[6:0] bit counts from each cs5490 are sorted in ascending order. figure 12 and figure 13 illustrate how phase sequence detection is performed. phase sequences a, b, and c for the default rising edge transition are illustrated in figure 12 . the pscnt[6:0] bits from the cs 5490 on phase a will have the lowest count, followed by the pscnt[6:0] bits from the cs5490 on phase b with the middle count, and the pscnt[6:0] bits from the cs5490 on phase c with the highest count. phase sequences c, b, and a for rising edge transition are illustrated in figure 13 . the pscnt[6:0] bits from the cs5490 on phase c will have the lowest count, followed by the pscnt[6:0] bits from the cs5490 on phase b with the middle count, and the pscnt[6:0] bits from the cs5490 on phase a with the highest count. figure 12. phase sequence a, b, c for rising edge transition -2 0 2 phase a channel -2 0 2 phase b channel -2 0 2 phase c channel write 0x16 to psdc register start on the falling edge on the rx pin stop stop stop phase c count phase b count phase a count a b c cs5490 ds982f2 23 5.8 temperature measurement the cs5490 has an internal temperature sensor, which is designed to measure temperature and optionally compensate for temperature drift of the voltage reference. temperature measurements are stored in the temperature register ( t ), which, by default, is configured to a range of 128c. the application program can change the scale and range of the temperature ( t ) register by changing the temperature gain ( t gain ) register and temperature offset ( t off ) register. the temperature ( t ) register updates every 2240 output word rate (owr) samples. the status0 register bit tup indicates when t is updated. 5.9 anti-creep the anti-creep (no-load threshold) is used to determine if a no-load condition is detected. the | p sum | and | q sum | are compared to the value in the no-load threshold ( load min ) register. if both | p sum | and | q sum | are less than this threshold, then p sum and q sum are forced to zero. if s sum is less than the value in load min register, then s sum is forced to zero. 5.10 register protection to prevent the critical configuration and calibration registers from unintended changes, the cs5490 provides two enhanced register protection mechanisms: write protection and automatic checksum calculation. 5.10.1 write protection setting the dsp_lck[4:0] bits in the reglock register to 0x16 enables the cs5490 dsp lockable registers to be write-protected from the calculation engine. setting the dsp_lck[4:0] bits to 0x09 disables the write-protection mode. setting the host_lck[4:0] bits in the reglock register to 0x16 enables the cs5490 host lockable registers to be write-protected from the serial interface. setting the host_lck[4:0] bits to 0x09 disables the write-protection mode. for registers that are dsp lockable, host lockable, or both, refer to sections 6.2 hardware registers summary (page 0) on page 26, 6.3 software registers summary (page 16) on page 28, and 6.4 software registers summary (page 17) on page 29. 5.10.2 register checksum all the configuration and ca libration registers are protected by checksum, if enabled. refer to sections 6.2 hardware registers summary (page 0) on page 26, 6.3 software registers summary (page 16) on page 28, and 6.4 software registers summary (page 17) on page 29. the checksum for all registers marked with an asterisk symbol (*) is comput ed at the rate of owr. the checksum result is stored in the regchk register. after the cs5490 has been fully configured and loaded with the calibrations, the host mi crocontroller should keep a copy of the checksum ( regchk_copy ) in its memory. in normal operation, the host microcontroller can read the regchk register and compare it with the saved copy of the regchk register. if the two values mismatch, a reload of configurations and calibrations into the cs5490 is necessary. the automatic checksum com putation can be disabled by setting the reg_csum_off bit in the config2 register. -2 0 2 phase a channel -2 0 2 phase b channel -2 0 2 phase c channel stop stop stop phase c count phase b count phase a count a b c write 0x16 to psdc register start on the falling edge on the rx pin figure 13. phase sequence c, b, a for rising edge transition cs5490 24 ds982f2 6. host commands and registers 6.1 host commands the first byte sent to the cs5490 rx pin contains the host command. four types of host commands are required to read and write registers and instruct the calculation engine. the two most significant bits (msbs) of the host command defines the function to be performed. the following table depicts the types of commands. table 2. command format 6.1.1 memory access commands the cs5490 memory has 12-bit addresses and is organized as p 5 p 4 p 3 p 2 p 1 p 0 a 5 a 4 a 3 a 2 a 1 a 0 in 64 pages of 64 addresses each. the higher 6 bits specify the page number. the lower 6 bits specify the address within the selected page. 6.1.1.1 page select a page select command is designated by setting the two msbs of the command to binary ?10?. the page select command provides the cs5490 with the page number of the register to access . register read and write commands access 1 of 64 registers within a specified page. subsequent register reads and writes can be performed once the page has been selected. figure 14. byte sequence for page select 6.1.1.2 register read a register read is designated by setting the two msbs of the command to binary ?00?. the lower 6 bits of the read register command are the lower 6 bits of the 12-bit register address. after the register read command has been received, the cs5490 will send 3 bytes of register data onto the tx pin. figure 15. byte sequence for register read 6.1.1.3 register write a register write command is designated by setting the two msbs of the command to binary ?01?. the lower 6 bits of the register write command are the lower 6 bits of the 12-bit register addres s. a register write command must be followed by 3 bytes of data. figure 16. byte sequence for register write 6.1.2 instructions an instruction command is designated by setting the two msbs of the command to binary '11'. an instruction command will interrupt any pr ocess currently running and initiate a new process in the cs5490. figure 17. byte sequence for instructions these new processes include calibration, power control, and soft reset. the following table depicts the types of instructions. note that when the cs5490 is in continuous conversion mode, an unexpected or invalid instruction command could cause the device to stop continuous conversion and enter an unexpected operation mode. the host processor should keep monitoring the cs5490 operation status and react accordingly. table 3. instruction format function binary value note register read 0 0 a 5 a 4 a 3 a 2 a 1 a 0 a [5:0] specifies the register address. register write 0 1 a 5 a 4 a 3 a 2 a 1 a 0 page select 1 0 p 5 p 4 p 3 p 2 p 1 p 0 p [5:0] specifies the page. instruction 1 1 c 5 c 4 c 3 c 2 c 1 c 0 c [5:0] specifies the instruction. rx page select cmd . tx rx data data data read cmd . function binary value note controls 0 c 4 c 3 c 2 c 1 c 0 0 00001 - software reset 0 00010 - standby 0 00011 - wakeup 0 10100 - single conv. 0 10101 - continuous conv. 0 11000 - halt conv. c [5] specifies the instruction type: 0 = controls 1 = calibrations calibration 1 c 4 c 3 c 2 c 1 c 0 1 00 c 2 c 1 c 0 dc offset 1 10 c 2 c 1 c 0 ac offset* 1 11 c 2 c 1 c 0 gain * ac offset calibration valid only for current channel. for calibration, c [4:3] specifies the type of cali- bration. 1c 4 c 3 c 2 c 1 c 0 1 c 4 c 3 0 0 1 i 1 c 4 c 3 0 1 0 v 1 c 4 c 3 1 1 0 i & v for calibration, c [2:0] specifies the channel(s). rx data data data write cmd. rx instruction cs5490 ds982f2 25 6.1.3 checksum to improve the communicati on reliability on the serial interface, the cs5490 provides a checksum mechanism on transmitted and received signals. checksum is disabled by default but can be enabled by setting the appropriate bit in the serialctrl register. when enabled, both host and cs5490 are expected to send one additional checksum byte after the normal command byte and applicable 3-byte register data have been transmitted. the checksum is calculated by subtracting each transmit byte from 0xff. any overflow is truncated and the result wraps. the cs5490 executes the command only if the checksum tran smitted by the host matches the checksum calculated loca lly. otherwise, it sets a status bit (rx_csum_err in status0 register), ignores the command, and clears the serial interface in preparation for the next transmission. figure 18. byte sequence for checksum 6.1.4 serial time out in case a transaction from the host is not completed (for example, a data byte is missing in a register write), a time out circuit will reset the interface after 128ms. this will require that each byte be sent from the host within 128ms of the previous byte. rx checksum page select cmd . tx rx checksum data data data checksum read cmd . rx data data data checksum write cmd. rx checksum instruction page select instruction read command write command cs5490 26 ds982f2 6.2 hardware regist ers summary (page 0) address 2 ra[5:0] name description 1 dsp 3 host 3 default 0* 00 0000 config0 configuration 0 y y 0x c0 2000 1* 00 0001 config1 configuration 1 y y 0x 00 eeee 2 00 0010 - reserved - 3* 00 0011 mask interrupt mask y y 0x 00 0000 4 00 0100 - reserved - - 5* 00 0101 pc phase compensation control y y 0x 00 0000 6 00 0110 - reserved - - 7* 00 0111 serialctrl uart control y y 0x 02 004d 8* 00 1000 pulsewidth energy pulse width y y 0x 00 0001 9* 00 1001 pulsectrl energy pulse control y y 0x 00 0000 10 00 1010 - reserved - - 11 00 1011 - reserved - - 12 00 1100 - reserved - - 13 00 1101 - reserved - 14 00 1110 - reserved - - 15 00 1111 - reserved - - 16 01 0000 - reserved - - 17 01 0001 - reserved - - 18 01 0010 - reserved - - 19 01 0011 - reserved - - 20 01 0100 - reserved - - 21 01 0101 - reserved - - 22 01 0110 - reserved - - 23 01 0111 status0 interrupt status n n 0x 80 0000 24 01 1000 status1 chip status 1 n n 0x 80 1800 25 01 1001 status2 chip status 2 n n 0x 00 0000 26 01 1010 - reserved - - 27 01 1011 - reserved - - 28 01 1100 - reserved - - 29 01 1101 - reserved - - 30 01 1110 - reserved - - 31 01 1111 - reserved - - 32 10 0000 - reserved - - 33 10 0001 - reserved - - 34* 10 0010 reglock register lock control n n 0x 00 0000 35 10 0011 - reserved - - 36 10 0100 v peak peak voltage n y 0x 00 0000 37 10 0101 i peak peak current n y 0x 00 0000 38 10 0110 - reserved - - 39 10 0111 - reserved - - 40 10 1000 - reserved - - 41 10 1001 - reserved - - 42 10 1010 - reserved - - 43 10 1011 - reserved - - 44 10 1100 - reserved - - 45 10 1101 - reserved - - 46 10 1110 - reserved - - 47 10 1111 - reserved - - 48 11 0000 psdc phase sequence detection & control n y 0x 00 0000 49 11 0001 - reserved - - 50 11 0010 - reserved - - 51 11 0011 - reserved - - 52 11 0100 - reserved - - cs5490 ds982f2 27 53 11 0101 - reserved - - 54 11 0110 - reserved - - 55 11 0111 zx num num. zero crosses used for line freq. y y 0x00 0064 56 11 1000 - reserved - - 57 11 1001 - reserved - - 58 11 1010 - reserved - - 59 11 1011 - reserved - - 60 11 1100 - reserved - - 61 11 1101 - reserved - - 62 11 1110 - reserved - - 63 11 1111 - reserved - - notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5490 28 ds982f2 6.3 software regist ers summary (page 16) address 2 ra[5:0] name description 1 dsp 3 host 3 default 0* 00 0000 config2 configuration 2 y y 0x 10 0200 1 00 0001 regchk register checksum n y 0x 00 0000 2 00 0010 i i instantaneous current n y 0x 00 0000 3 00 0011 v v instantaneous voltage n y 0x 00 0000 4 00 0100 p instantaneous power n y 0x 00 0000 5 00 0101 p avg active power n y 0x 00 0000 6 00 0110 i rms i rms current n y 0x 00 0000 7 00 0111 v rms v rms voltage n y 0x 00 0000 8 00 1000 - reserved - 9 00 1001 - reserved - 10 00 1010 - reserved - 11 00 1011 - reserved - 12 00 1100 - reserved - 13 00 1101 - reserved - 14 00 1110 q avg reactive power n y 0x 00 0000 15 00 1111 q instantaneous reactive power n y 0x 00 0000 16 01 0000 - reserved - 17 01 0001 - reserved - 18 01 0010 - reserved - 19 01 0011 - reserved - 20 01 0100 s apparent power n y 0x 00 0000 21 01 0101 pf power factor n y 0x 00 0000 22 01 0110 - reserved - 23 01 0111 - reserved - 24 01 1000 - reserved - 25 01 1001 - reserved - 26 01 1010 - reserved - 27 01 1011 t temperature n y 0x 00 0000 28 01 1100 - reserved - 29 01 1101 p sum total active power n y 0x 00 0000 30 01 1110 s sum total apparent power n y 0x 00 0000 31 01 1111 q sum total reactive power n y 0x 00 0000 32* 10 0000 i dcoff i dc offset y y 0x 00 0000 33* 10 0001 i gain i gain y y 0x 40 0000 34* 10 0010 v dcoff v dc offset y y 0x 00 0000 35* 10 0011 v gain v gain y y 0x 40 0000 36* 10 0100 p off instantaneous power offset 0x 00 0000 37* 10 0101 i acoff i ac offset y y 0x 00 0000 38* 10 0110 - reserved - 39* 10 0111 - reserved - 40* 10 1000 - reserved - 41* 10 1001 - reserved - 42* 10 1010 - reserved - 43* 10 1011 - reserved - 44* 10 1100 - reserved - 45* 10 1101 - reserved - 46 10 1110 - reserved - 47 10 1111 - reserved - 48 11 0000 - reserved - 49 11 0001 epsilon ratio of line to sample frequency n y 0x 01 999a 50* 11 0010 - reserved - 51* 11 0011 samplecount sample count n y 0x 00 0fa0 52 11 0100 - reserved - cs5490 ds982f2 29 53 11 0101 - reserved - 54* 11 0110 t gain temperature gain y y 0x 06 b716 55* 11 0111 t off temperature offset y y 0x d5 3998 56* 11 1000 - reserved - 57 11 1001 t settle filter settling time to conv. startup y y 0x 00 001e 58* 11 1010 load min no load threshold y y 0x 00 0000 59* 11 1011 - reserved - 60* 11 1100 sys gain system gain n y 0x 50 0000 61 11 1101 time system time (in samples) n y 0x 00 0000 62 11 1110 - reserved - 63 11 1111 - reserved - notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. 6.4 software regist ers summary (page 17) address 2 ra[5:0] name description 1 dsp 3 host 3 default 0* 00 0000 vsag dur v sag duration y y 0x 00 0000 1* 00 0001 vsag level v sag level y y 0x 00 0000 2 00 0010 - reserved - 3 00 0011 - reserved - 4* 00 0100 iover dur i overcurrent duration y y 0x 00 0000 5* 00 0101 iover level i overcurrent level y y 0x 7f ffff 6 00 0110 - reserved - 7 00 0111 - reserved - 8* 00 1000 - reserved - 9* 00 1001 - reserved - 10 00 1010 - reserved - 11 00 1011 - reserved - 12* 00 1100 - reserved - 13* 00 1101 - reserved - 14 00 1110 - reserved - 15 00 1111 - reserved - 16 01 0000 - reserved - 17 01 0001 - reserved - 18 01 0010 - reserved - 19 01 0011 - reserved - 20 01 0100 - reserved - 21 01 0101 - reserved - 22 01 0110 - reserved - 23 01 0111 - reserved - 24 01 1000 - reserved - 25 01 1001 - reserved - 26 01 1010 - reserved - 27 01 1011 - reserved - 28 01 1100 - reserved - 29 01 1101 - reserved - 30 01 1110 - reserved - 31 01 1111 - reserved - notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5490 30 ds982f2 6.5 software regist ers summary (page 18) address 2 ra[5:0] name description 1 dsp 3 host 3 default 24* 01 1000 izx level i-channel zero-crossing threshold y y 0x 10 0000 25 01 1001 - reserved - 26 01 1010 - reserved - 27 01 1011 - reserved - 28* 01 1100 pulserate energy pulse rate y y 0x 80 0000 29 01 1101 - reserved - 30 01 1110 - reserved - 31 01 1111 - reserved - 32 10 0000 - reserved - 33 10 0001 - reserved - 34 10 0010 - reserved - 35 10 0011 - reserved - 36 10 0100 - reserved - 37 10 0101 - reserved - 38 10 0110 - reserved - 39 10 0111 - reserved - 40 10 1000 - reserved - 41 10 1001 - reserved - 42 10 1010 - reserved - 43* 10 1011 int gain rogowski coil integrator gain y y 0x 14 3958 44 10 1100 - reserved - 45 10 1101 - reserved - 46* 10 1110 vswell dur v swell duration y y 0x 00 0000 47* 10 1111 vswell level v swell level y y 0x 7f ffff 48 11 0000 - reserved - 49 11 0001 - reserved - 50* 11 0010 - reserved - 51* 11 0011 - reserved - 52 11 0100 - reserved - 53 11 0101 - reserved - 54 11 0110 - reserved - 55 11 0111 - reserved - 56 11 1000 - reserved - 57 11 1001 - reserved - 58* 11 1010 vzx level v-channel zero-crossing threshold y y 0x 10 0000 59 11 1011 - reserved - 60 11 1100 - reserved - 61 11 1101 - reserved - 62* 11 1110 cyclecount line cycle count n y 0x 00 0064 63* 11 1111 scale scale value for i-channel gain calibration y y 0x 4c cccc notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5490 ds982f2 31 6.6 register descriptions 21. ?default? = bit states after power-on or reset 22. do not write a ?1? to any unpublished regi ster bit or to a bit published as ?0?. 23. do not write a ?0? to any bit published as ?1?. 24. do not write to any unpublished register address. 6.6.1 configuration 0 (config0) ? page 0, address 0 default = 0xc0 2000 [23:9] reserved. int_pol interrupt polarity. 0 = active low (default) 1 = active high [7:6] reserved. ipga[1:0] select pga gain for i channel. 00 = gain (default) 10 = 50x gain [3] reserved. no_osc disable crystal oscillator (m aking xin a logic-level input). 0 = crystal oscillator enabled (default) 1 = crystal oscillator disabled 23 22 21 20 19 18 17 16 1100 - -- - 15 14 13 12 11 10 9 8 -01- - --int_pol 76543210 - - ipga[1] ipga[0] - no_osc 0 0 cs5490 32 ds982f2 6.6.2 configuration 1 (config1) ? page 0, address 1 default = 0x00 eeee [23:21] reserved. epg_on enable epg block. 0 = disable energy pulse generation block (default) 1 = enable energy pulse generation block [19:17] reserved. do_od allow the do pin to be an open-drain output. 0 = normal output (default) 1 = open-drain output [15:4] reserved. domode[3:0] output control for do pin. 0000 = energy pulse generation (epg) block output 0001 = reserved 0010 = reserved 0011 = reserved 0100 = p sign 0101 = reserved 0110 = p sum sign 0111 = q sign 1000 = reserved 1001 = q sum sign 1010 = reserved 1011 = v zero-crossing 1100 = i zero-crossing 1101 = reserved 1110 = hi-z, pin not driven (default) 1111 = interrupt 23 22 21 20 19 18 17 16 000epg_on000do_od 15 14 13 12 11 10 9 8 11101110 76543210 1 1 1 0 domode[3] domode[2] domode[1] domode[0] cs5490 ds982f2 33 6.6.3 configuration 2 (config2) ? page 16, address 0 default = 0x10 0200 [23] reserved. pos positive energy only. supp ress negative values in p avg . if a negative value is calculated, a zero result will be stored. 0 = positive and negative energy (default) 1 = positive energy only [21:15] reserved. apcm selects the apparent power calculation method. 0 = v rms x i rms (default) 1 = sqrt(p avg 2 + q avg 2 ) [13] reserved. zx_lpf enable lpf in zero-cross detect. 0 = lpf disabled (default) 1 = lpf enabled avg_mode select averaging mode for low-rate calculations. 0 = use samplecount (default) 1 = use cyclecount reg_csum_off disable checksum on critical registers. 0 = enable checksum on critical registers (default) 1 = disable checksum on critical registers afc enables automatic line frequency measurement which sets epsilon every time a new line frequency measurement completes. epsilon is used to control the gain of 90 phase shift integrator used in quadrature power calculations. 0 = disable automatic line frequency measurement 1 = enable automatic line fr equency measurement (default) [8:5] reserved. iflt[1:0] filter enable for current channel. 00 = no filter (default) 01 = high-pass filter (hpf) on current channel 10 = phase-matching filter (pmf) on current channel 11 = rogowski coil integrator (int) on current channel vflt[1:0] filter enable for voltage channel. 00 = no filter (default) 01 = high-pass filter (hpf) on voltage channel 10 = phase-matching filter (pmf) on voltage channel 11 = reserved iir_off[0] bypass iir filter. 0 = do not bypass iir filter (default) 1 = bypass iir filter 23 22 21 20 19 18 17 16 -pos- 1 - 0 0- 15 14 13 12 11 10 9 8 - apcm - zx_lpf avg_mode reg_csum_off afc 0 76543 2 10 0 0 0 iflt[1] iflt[0] vflt[1] vflt[0] iir_off cs5490 34 ds982f2 6.6.4 phase compensation (pc) ? page 0, address 5 default = 0x00 0000 [23:22] reserved. cpcc[1:0] coarse phase compensation control for i & v. 00 = no extra delay 01 = 1 owr delay in current channel 10 = 1 owr delay in voltage channel 11 = 2 owr delay in voltage channel [19:9] reserved. fpcc[8:0] fine phase compensation control for i & v. sets a delay in current, relative to voltage. resolution: 0.008789 at 50hz and 0.010547 at 60hz (owr = 4000) 6.6.5 uart control (serialctrl) ? page 0, address 7 default = 0x02 004d [23:19] reserved. rx_pu_off disable the pull-up resistor on the rx input pin. 0 = pull-up resistor enabled (default) 1 = pull-up resistor disabled rx_csum_off disable the checksum on serial port data. 0 = enable checksum 1 = disable checksum (default) [16] reserved. br[15:0] baud rate (serial bit rate). br[15:0] = baud rate x 524288 / mclk 23 22 21 20 19 18 17 16 - - cpcc[1] cpcc[0] - - - - 15 14 13 12 11 10 9 8 -------fpcc[8] 76543210 fpcc[7] fpcc[6] fpcc[5] fpcc[4 ] fpcc[3] fpcc[2] fpcc[1] fpcc[0] 23 22 21 20 19 18 17 16 - - - - - rx_pu_off rx_csum_off - 15 14 13 12 11 10 9 8 br[15] br[14] br[13] br[12] br[11] br[10] br[9] br[8] 765432 10 br[7] br[6] br[5] br[4] br[3] br[2] br[1] br[0] cs5490 ds982f2 35 6.6.6 pulse output width (pulsewidth) ? page 0, address 8 default = 0x00 0001 (265.6s at owr = 4khz) pulsewidth sets the energy pulse frequency range and the duration of energy pulses. the actual pulse duration is 250s plus the contents of pulsewidth divided by 64,000. pulsewidth is an inte- ger in the range of 1 to 65,535. [23:20] reserved. freq_rng[19:16] energy pulse ( pulserate ) frequency range for 0.1% resolution. 0000 = freq. range: 2 khz ? 0.238 hz (default) 0001 = freq. range: 1 khz ? 0.1192 hz 0010 = freq. range: 500 hz ? 0.0596 hz 0011 = freq. range: 250hz?0.0298hz 0100 = freq. range: 125 hz ? 0.0149 hz 0101 = freq. range: 62.5 hz ? 0.00745 hz 0110 = freq. range: 31.25 hz ? 0.003725 hz 0111 = freq. range: 15.625 hz ? 0.0018626 hz 1000 = freq. range: 7.8125 hz ? 0.000931323 hz 1001 = freq. range: 3.90625 hz ? 0.000465661 hz 1010 = reserved ... 1111 = reserved pw[15:0] energy pulse width. 6.6.7 pulse output rate (pulserate) ? page 18, address 28 default= 0x80 0000 pulserate sets the full-scale frequency for the energy pulse output. for a 4 khz owr rate, the ma ximum pulse rate is 2 khz. it is a tw o's complement value in the range of -1 ? value ? 1, with the binary point to the left of the msb. refer to section 5.5 energy pulse generation on page 19 for more information. 23 22 21 20 19 18 17 16 - - - - freq_rng[3] freq_rng[2] freq_rng[1] freq_rng[0] 15 14 13 12 11 10 9 8 pw[15] pw[14] pw[13] pw[12] pw[11] pw[10] pw[9] pw[8] 76543210 pw[7] pw[6] pw[5] pw[4] pw[3] pw[2] pw[1] pw[0] msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 36 ds982f2 6.6.8 pulse output control (pulsectrl) ? page 0, address 9 default = 0x00 0000 this register controls the input to t he energy pulse generation (epg) block. [23:4] reserved. epgin[3:0] selects the input to the energy pulse generation (epg) block. 0000 = p avg (default) 0001 = reserved 0010 = p sum 0011 = q avg 0100 = reserved 0101 = q sum 0110 = s 0111 = reserved 1000 = s sum 1001 = unused ... 1111 = unused 6.6.9 register lock control (reglock) ? page 0, address 34 default = 0x00 0000 [23:13] reserved. dsp_lck[12:8] dsp_lck[4:0] = 0x16 sets the dsp lockable registers to be write protected from the cs5490 internal calculation engine. writing 0x09 unlocks the registers. [7:5] reserved. host_lck[4:0] host_lck[4:0] = 0x16 sets all the registers except reglock , status0 , status1 , and status2 to be write protected from the serial in terface. writing 0x09 unlocks the registers. 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 00000000 76543210 0 0 0 0 epgin[3] epgin[2 ] epgin[1] epgin[0] 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - dsp_lck[4] dsp_lck[3] dsp _lck[2] dsp_lck[1] dsp_lck[0] 76543210 - - - host_lck[4] host_lck[3] host _lck[2] host_lck[1] host_lck[0] cs5490 ds982f2 37 6.6.10 phase sequence detection and control (psdc) ? page 0, address 48 default = 0x00 0000 done indicates valid count va lues reside in pscnt[6:0]. 0 = invalid values in pscnt[6:0]. (default) 1 = valid values in pscnt[6:0]. pscnt[6:0] registers the number of owr samples fr om the start time to the time when the next zero crossing is detected. [15:6] reserved. dir set the zero-crossing edge dire ction which will stop pscnt count. 0 = stop count at negative to positive zero-crossing - rising edge. (default) 1 = stop count at positive to nega tive zero-crossing - falling edge. code[4:0] write 10110 to this location to enable the phase sequence detection. 6.6.11 checksum of critical registers (regchk) ? page 16, address 1 default = 0x00 0000 this register contains the ch ecksum of critical registers. 23 22 21 20 19 18 17 16 done pscnt[6] pscnt[5] pscnt[4] psc nt[3] pscnt[2] pscnt[1] pscnt[0] 15 14 13 12 11 10 9 8 ------ -- 765432 10 - - dir code[4] code[3] code[2] code[1] code[0] msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5490 38 ds982f2 6.6.12 interrupt status (status0) ? page 0, address 23 default = 0x 00 0000 the status0 register indicates a variety of conditions within the chip. writing a one to a status0 register bit will clear that bit. writ ing a zero to any bit has no effect. drdy data ready. during conversion, this bit indicates that low-rate results have been updated. it indicates completion of other host instruction and the reset sequence. crdy conversion ready. indicates that sample rate (output word rate) results have been updat- ed. wof watchdog timer overflow. [20:19] reserved. mips mips overflow. sets when the calculation engine has not comp leted processing a sample before the next one arrives. [17] reserved. vswell voltage channel swell event detected. [15] reserved. por power out of range. sets when the measured power would cause the p register to overflow. [13] reserved. ior current out of range. set when t he measured current would cause the i register to overflow. [11] reserved. vor voltage out of range. set when t he measured voltage would cause the v register to over- flow. [7] reserved. ioc i overcurrent. [9] reserved. vsag voltage channel sag event detected. tup temperature updated. indicates when the temperature register ( t ) has been updated. fup frequency updated. indicates the epsilon register has been updated. ic invalid command has been received. rx_csum_err received data checksum error. sets to one automatically if checksum error is detected on serial port received data. rx_to sdi/rx time out. sets to one auto matically when sdi/rx time out occurs. 23 22 21 20 19 18 17 16 drdy crdy wof - - mips - vswell 15 14 13 12 11 10 9 8 - por - ior - vor - ioc 76543 2 10 - vsag tup fup ic rx_csum_err - rx_to cs5490 ds982f2 39 6.6.13 interrupt mask (mask) ? page 0, address 3 default = 0x00 0000 the mask register is used to cont rol the activation of the int pin. writing a '1' to a mask register bit will allow the corresponding status0 register bit to activate the int pin when set. [23:0] enable/disable (mask) interrupts. 0 = interrupt disabled (default) 1 = interrupt enabled 6.6.14 chip status 1 (status1) ? page 0, address 24 default = 0x00 0000 this register indicates a variety of conditions within the chip. [23:16] reserved. lcom[15:8] indicates the value of the last serial command executed. [7:4] reserved. tod modulator oscillati on has been detected in the temperature adc. vod modulator oscillation has been detected in the voltage adc. [1] reserved. iod modulator oscillation has been detected in the current adc. 23 22 21 20 19 18 17 16 drdy crdy wof - - mips 0 vswell 15 14 13 12 11 10 9 8 0 por 0 ior 0 vor 0 ioc 76543 2 10 0 vsag tup fup ic rx_csum_err - rx_to 23 22 21 20 19 18 17 16 ------ 15 14 13 12 11 10 9 8 lcom[7] lcom[6] lcom[5] lcom[4] lcom[3] lcom[2] lcom[1] lcom[0] 76543210 ----todvod-iod cs5490 40 ds982f2 6.6.15 chip status 2 (status2) ? page 0, address 25 default = 0x00 0000 this register indicates a variety of conditions within the chip. [23:6] reserved. qsum_sign indicates the sign of the value contained in q sum . 0 = positive value 1 = negative value [4] reserved. q_sign indicates the sign of the value contained in q avg . 0 = positive value 1 = negative value psum_sign indicates the sign of the value contained in p sum . 0 = positive value 1 = negative value [1] reserved. p_sign indicates the sign of the value contained in p avg . 0 = positive value 1 = negative value 6.6.16 line to sample frequency ratio (epsilon) ? page 16, address 49 default = 0x01 999a (0.0125 or 50hz/4.0khz) epsilon is the ratio of the input line frequency to the output word rate (owr). it can either be written by the application program or calculated automatically fr om the line frequency (from the voltage channel input) using the afc bit in the config2 register. it is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - qsum_sign - q_sign psum_sign - p_sign msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 ds982f2 41 6.6.17 no load threshold (load min ) ? page 16, address 58 default = 0x00 0000 load min is used to set the no-load thre shold for the anti -creep function. when the magnitudes of p sum and q sum are less than load min , p sum and q sum are forced to zero. when the magnitude of s sum is less than load min , s sum is forced to zero. load min is a two?s complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.18 sample count (samplecount) ? page 16, address 51 default = 0x00 0fa0 (4000) determines the number of output word rate (owr) samples to use in calcul ating low-rate results. samplecount ( n ) is an integer in the range of 100 to 8,388, 607. values less than 100 should not be used. 6.6.19 cycle count (cyclecount) ? page 18, address 62 default = 0x00 0064 (100) determines the number of half-line cycles to use in calcul ating low-rate results when the cs5490 is in line-cy- cle synchronized averaging mode. cyclecount is an integer in the range of 1 to 8,388,607. zero should not be used. 6.6.20 filter settling time for conversion startup (t settle ) ? page 16, address 57 default = 0x00 001e (30) sets the number of output word rate (owr) samples that will be used to allo w filters to settle at the beginning of conversion and calibration commands. this is an integer in the range of 0 to 16,777,215 samples. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5490 42 ds982f2 6.6.21 system gain (sys gain ) ? page 16, address 60 default = 0x50 0000 (1.25) system gain ( sys gain ) is applied to all channels. by default, sys gain = 1.25, but can be finely adjusted to compensa te for voltage reference error. it is a two's complement value in the range of -2.0 ? value ? 2.0, with the binary point to the right of the second msb. val- ues should be kept within 5% of 1.25. 6.6.22 rogowski coil integrator gain (int gain ) ? page 18, address 43 default = 0x14 3958 gain for the rogowski coil integrator. this must be programmed accordingly for 50hz and 60hz (0.158 for 50hz, 0.1875 for 60hz). this is a two?s complement value in the range of -1.0 ? value ? 1.0, with the binary poin t to the right of the msb. negative values are not used. 6.6.23 system time (time) ? page 16, address 61 default = 0x00 0000 system time ( time ) is measured in output word rate (owr) samples. this is an unsigned integer in the range of 0 to 16 ,777,215 samples. at owr = 4.0 khz, owr will overflow every 1 hour, 9 minutes, 54 seconds. time can be used by the application to manage real-time events. 6.6.24 voltage sag duration (vsag dur ) ? page 17, address 0 default = 0x00 0000 voltage sag duration, vsag dur , determines the co unt of output word rate (o wr) samples utilized to deter- mine a sag event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. msb lsb -(2 1 )2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5490 ds982f2 43 6.6.25 voltage sag level (vsag level ) ? page 17, address 1 default = 0x00 0000 voltage sag level, vsag level , establishes an input level below which a sag event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.26 current overcurrent duration (iover dur ) ? page 17, address 4 default = 0x00 0000 overcurrent duration, iover dur , determines the count of output word rate (owr) samples utilized to deter- mine an overcurrent event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.27 current overcurrent level (iover level ) ? page 17, address 5 default = 0x7f ffff overcurrent level, iover level , establishes an input level above which an overcurrent event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.28 voltage swell duration (vswell dur ) ? page 18, address 46 default = 0x00 0000 voltage swell duration, vswell dur , determines the count of output word rate (owr) samples used to deter- mine a swell event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5490 44 ds982f2 6.6.29 voltage swell level (vswell level ) ? page 18, address 47 default = 0x7f ffff voltage swell level, vswell level , establishes an input level above which a swell event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.30 instantaneous current (i) ? page 16, address 2 default = 0x00 0000 i contains instantaneous current measurements for current channel. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.31 instantaneous voltage (v) ? page 16, address 3 default = 0x00 0000 v contains instantaneous voltage measurements for voltage channel. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.32 instantaneous active power (p) ? page 16, address 4 default = 0x00 0000 p contains instantaneous power measurements for current and voltage channels. values in registers i and v are multiplied to generate th is value. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 ds982f2 45 6.6.33 active power (p avg ) ? page 16, address 5 default = 0x00 0000 instantaneous power is averaged over each low-rate interval ( samplecount samples) and then added with power offset ( p off ) to compute active power ( p avg ). this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.34 rms current (i rms ) ? page 16, address 6 default = 0x00 0000 i rms contains the root mean square (rms) values of i , calculated during each low-rate interval. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.35 rms voltage (v rms ) ? page 16, address 7 default = 0x00 0000 v rms contains the root mean square (rms) value of v , calculated during each low-rate interval. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.36 reactive power (q avg ) ? page 16, address 14 default = 0x00 0000 reactive power ( q avg ) is q averaged over each low-rate interval ( samplecount samples) and corrected by q off . this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 46 ds982f2 6.6.37 instantaneous quadrature power (q) ? page 16, address 15 default = 0x00 0000 instantaneous qu adrature power, q , the product of v shifted 90 and i . this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.38 peak current (i peak ) ? page 0, address 37 default = 0x00 0000 peak current ( i peak ) contains the value of the instantaneous cu rrent 1 sample with the greatest magnitude detected during the last low-rate interval. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.39 peak voltage (v peak ) ? page 0, address 36 default = 0x00 0000 peak voltage ( v peak ) contains the value of the instantaneous voltage sample with the greatest magnitude detected during the last low-rate interval. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.40 apparent power (s) ? page 16, address 20 default = 0x00 0000 apparent power 1 ( s ) is the product of v rms and i rms or sqrt( p avg 2 + q avg 2 ). this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 ds982f2 47 6.6.41 power factor (pf) ? page 16, address 21 default = 0x00 0000 power factor ( pf ) is calculated by dividing active power ( p avg ) by apparent power ( s ). the sign is determined by the active power ( p avg ) sign. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.42 temperature (t) ? page 16, address 27 default = 0 t contains results from the on- chip temperature measurement. by default, t uses the celsius scale and is a two's complement value in the range of -128.0 ? value ? 128.0 (c), with the binary point to the right of bit 16. t can be rescaled by the application using the t gain and t off registers. 6.6.43 total active power (p sum ) ? page 16, address 29 default = 0 p sum =p avg this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.44 total apparent power (s sum ) ? page 16, address 30 default = 0 s sum =s this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 48 ds982f2 6.6.45 total reactive power (q sum ) ? page 16, address 31 default = 0 q sum =q avg this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.46 dc offset for current (i dcoff ) ? page 16, address 32 default = 0 dc offset registers i dcoff are initialized to zero on reset. during dc offset calibration, selected registers are written with the inverse of the dc offset measured. t he application program can al so write the dc offset reg- ister values. this is a two's comp lement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.47 dc offset for voltage (v dcoff ) ? page 16, address 34 default = 0 dc offset registers v dcoff are initialized to zero on reset. during dc offset calibration, selected registers are written with the inverse of the dc offset measured. t he application program can al so write the dc offset reg- ister values. it is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.48 gain for current (i gain ) ? page 16, address 33 default = 1.0 gain register i gain is initialized to 1.0 on rese t. during gain calibration, the i gain register is written with the multiplicative inverse of the gain measured. this is an unsigned fixed-point value in the range of 0 ? value ? 4.0, with the binary point to the right of the second msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 cs5490 ds982f2 49 6.6.49 gain for voltage (v gain ) ? page 16, address 35 default = 1.0 gain register v gain is initialized to 1.0 on rese t. during gain calibration, the v gain register is written with the multiplicative inverse of the gain measured. this is an unsigned fixed-point value in the range of 0 ? value ? 4.0, with the binary point to the right of the second msb. 6.6.50 average active power offset (p off ) ? page 16, address 36 default = 0 average active power offset ( p off ) is added to the averaged active power to yield p avg register results. it can be used to reduce systematic energy errors. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.51 average reactive power offset (q off ) ? page 16, address 38 default = 0x00 0000 average reactive power offset ( q off ) is added to the averaged active power to yield q avg register results. it can be used to reduce systematic energy errors . it is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.52 ac offset for current (i acoff ) ? page 16, address 37 default = 0 ac offset register i acoff is initialized to zero on re set. it is used to reduce syst ematic errors in the rms re- sults. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.53 temperature gain (t gain ) ? page 16, address 54 default = 0x 06 b716 register t gain is used to scale the temperature register ( t ), and is an unsigned fixed-point value in the range of 0.0 ? value ? 256.0, with the binary point to the right of bit 16. register t can be rescaled by the application using the t gain and t off registers. refer to section 7.3 tem- perature sensor calibration on page 53 for more information. msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 cs5490 50 ds982f2 6.6.54 temperature offset (t off ) ? page 16, address 55 default = 0xd5 3998 register t off is used to offset the temperature register ( t ), and is a two's complement value in the range of -128.0 ? value ? 128.0 (c), with the binary point to the right of bit 16. register t can be rescaled by the application using the t gain and t off registers. refer to section 7.3 tem- perature sensor calibration on page 53 for more information. 6.6.55 calibration scale (scale) ? page18, address 63 default = 0x4c cccc (0.6) the scale register is used in the gain calibration to set t he level of calibrate d results of i-channel rms. during gain calibration, the i rms results register is divided into the scale register. the quotient is put into the i gain register. it is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.56 zero-crossing number (zx num ) ? page 0, address 55 default = 0x00 0064 (100) zx num is the number of zero crossings used for line frequ ency measurement. it is an integer in the range of 1 to 8,388,607. zero should not be used. 6.6.57 v-channel zero- crossing threshold (vzx level ) ? page 18, address 58 default = 0x10 0000 (0.125) vzx level is the level that the peak instantaneous voltag e must exceed for the zero-crossing detection to function. this is a two's complement value in the range of -1.0 ? value<1.0, with the binary point to the right of the msb. negative values are not used. 6.6.58 i-channel zero-crossing threshold (izx level ) ? page 18, address 24 default = 0x10 0000 (0.125) izx level is the level that the peak instant aneous current must exceed for the zero-crossing detection to func- tion. this is a two's compleme nt value in the range of -1.0 ? value<1.0, with the binary point to the right of the msb. negative values are not used. msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5490 ds982f2 51 7. system calibration component tolerances, residual adc offset, and system noise require a meter that needs to be calibrated before it meets a specific accuracy requirement. the cs5490 provides an on-chip calibration algorithm to operate the system calibration quickly and easily. benefiting from the excellent linearity and low noise level of the cs5490, a cs5490 meter normally only needs one calibration at a single load point to achieve accurate measurements over the full load range. 7.1 calibration in general the cs5490 provides dc offset and gain calibration that can be applied to the instantaneous voltage and current measurements and ac offset calibration, which can only be applied to the current rms calculation. since the voltage and current channels have independent offset and gain registers, offset and gain calibration can be performed on any channel independently. the data flow of the calibration is shown in figure 19 . note that in figure 19 the ac offset registers and gain registers affect the output results differently than the dc offset registers. the dc offset and gain values are applied to the voltage/current signals early in the signal path; the dc offset register and gain register values affect all cs5490 results. this is not true for the ac offset correction. the ac offs et registers only affect the results of the rms current calculation. the cs5490 must be operating in its active state and ready to accept valid co mmands. refer to section 6.1.2 instructions on page 24 for different calibration commands. the value in the samplecount register determines the number ( n ) of output word rate (owr) samples that are averaged during a calibration. the calibration procedure takes the time of n + t settle owr samples. as n is increased, the calibration takes more time, but the accuracy of the calibration results tends to increase. the drdy bit in the status0 register will be set at the completion of calibration commands. if an overflow occurs during calibration, other status0 bits may be set as well. 7.1.1 offset calibration during offset calibrations, no line voltage or current should be applied to the meter; the differential signal on voltage inputs vin or current inputs iin of the cs5490 should be 0 volts. 7.1.1.1 dc offset calibration the dc offset calibration command measures and averages dc values read on specified voltage or current channels at zero input and stores the inverse result in the associated offset registers. this dc offset will be added to instanta neous measurements in subsequent conversions, removing the offset. the gain register for the channel being calibrated should be set to 1.0 prior to performing dc offset calibration. dc offset calibration is not required if the high-pass filter is enabled on that channel because the dc component will be removed by the high-pass filter. 7.1.1.2 ac offset calibration the ac offset calibration applies only to the current channel. it measures the residual rms values on the current channel at zero input and stores the squared v rms * , i rms * registers in modulator filter n ? * denotes readable/writable register ? applies only to the current path (i1, i2) ?? n ? n -1 ? n dc rms -1 rms 0. 6( scale * ? ) v * , i * , p * , q * registers i gain * , v gain * registers i dcoff * , v dco ff * registers i acoff * ? register figure 19. calibration data flow cs5490 52 ds982f2 result in the ac offset regi ster. this ac offset will be subtracted from rms measurements in subsequent conversions, removing the ac offset on the current channel. the ac offset register for the channel being calibrated should first be cleared prior to performing the calibration. the high-pass filter should be enabled if ac offset calibration is used. it is recommended that t settle be set to 2000ms before performing an ac offset calibration. note that the ac offset register holds the square of the rms value measured during calibration. therefore, it can hold a maximum rms noise of . this is the maximum rms noise that ac offset correction can remove. 7.1.2 gain calibration prior to executing the gain calibration command, gain registers for any path to be calibrated ( v gain , i gain ) should be set to ?1.0,? and t settle should be set to 2000 ms. for gain calibration, a reference signal must be applied to the meter. du ring gain calibration, the voltage rms result register ( v rms ) is divided into ?0.6,? and the current rms result register ( i rms ) is divided into the scale register. the quotient is put into the associated gain register. the gain calibration algorithm attempts to adjust the gain register ( v gain , i gain ) such that the voltage rms result register ( v rms ) equals ?0.6,? and the current rms result register ( i rms ) equals the scale register. note that for the gain calibration, there are limitations on choosing the reference level and the scale register value. using a reference or a scale that is too large or too small can cause register overflow during calibration or later during normal operation. either condition can set status register bits ior and vor. the maximum value that the gain register ca n attain is ?4.? using inappropriate reference levels or scale values may also cause the cs5490 to attempt to set the gain register higher than ?4.? t herefore, the gain calibration result will be invalid. the scale register is ?0.6? by default. the maximum voltage (u max volts) and current (i max amps) of the meter should be used as the reference signal level if the scale register is ?0.6.? after gain calibration, ?0.6? of the v rms ( i rms ) registers represents u max volts (i max amps) for the line voltage (load current); ?0.36? of the p avg , q avg , or s register represents u max i max watts, vars, or vas for the active, reactive, or apparent power. if the calibration is performed with u max volts and i cal amps and i cal cs5490 ds982f2 53 6) if the phase offset is negative, then the delay should be added only to the current channel. otherwise, add more delay to the voltage channel than to the current channel to compensate for a positive phase offset. once the phase offset is known, the cpcc and fpcc bits for that channel are calculated and programmed in the pc register. cpcc bits are used if either ? the phase offset is more than 1 output word rate (owr) sample. ? more delay is needed on the voltage channel. the compensation resolution is 0.008789 at 50hz and 0.010547 at 60hz at an owr of 4000hz. 7.3 temperature sensor calibration temperature sensor calibration involves the adjustment of two parameters: temperature gain ( t gain ) and temperature offset (t off ). before calibration, t gain must be set to 1.0 (0x 01 0000), and t off must be set to 0.0 (0x 00 0000). 7.3.1 temperature offset and gain calibration to obtain the optimal temperature offset (t off ) register value and temperature (t gain ) register value, it is necessary to measure the temperature ( t ) register at a minimum of two points (t1 and t2) across the meter operating temperature range. the two temperature points must be far enough apart to yield reasonable accuracy, for example 25 c and 85 c. obtain a linear fit of these points ( ), where the slope (m) and intercept (b) can be obtained. figure 20. t register vs. force temp t off and t gain are calculated using the equations below: ymxb + ? = force temperature ( c) t register value y = m ? x + b m b t1 t2 t off b m ---- - = t gain m = cs5490 54 ds982f2 8. basic application circuits the cs5490 is configured to measure power in a single-phase, two-wire single voltage and current system, as illustrated in figure 21 . in this diagram, a current transformer (ct) is used to sense the line load current, and a resistive voltage divider is used to sense the line voltage. ct cs5490 line n vin- vin+ iin+ iin- application processor reset rx tx gnda do vdda +3.3v 0.1f 0.1f +3.3v vddd +3.3v vref- vref+ 0.1f wh 4.096 mhz xin xout 1k mode 5 x250k 1k load 0.1 f 10k +3 .3v 27nf 27nf 1k 1k ? r burden ? r burden 27nf 27nf figure 21. typical connection diagram (single-phase, two-wire, power meter) cs5490 ds982f2 55 9. package dimensions notes: 1. controlling dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m. 3. this drawing conforms to jedec outline ms-012, variation ac for standard 16 soic narrow body. 4. recommended reflow profile is per jedec/ipc j-std-020. 16 soic (150 mil body) package drawing mm inch dimension min nom max min nom max a - - - - 1.75 - - - - 0.069 a1 0.10 - - 0.25 0.004 - - 0.010 b 0.31 - - 0.51 0.012 - - 0.020 c 0.10 - - 0.25 0.004 - - 0.010 d 9.90 bsc 0.390 bsc e 6.00 bsc 0.236 bsc e1 3.90 bsc 0.154 bsc e 1.27 bsc 0.05 bsc l 0.40 - - 1.27 0.016 - - 0.050 0 - - 8 0 - - 8 aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010 cs5490 56 ds982f2 10. ordering information 11. environmental, manufac turing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 12. revision history ordering number container temperature package cs5490-isz bulk -40 to +85 c 16-pin soic, lead (pb) free CS5490-ISZR tape & reel part number peak reflow temp msl rating* max floor life cs5490-isz 260 c 3 7 days revision date changes pp1 apr 2012 preliminary release. f1 apr 2012 edited for content and clarity. f2 jun 2012 updated ordering information. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in products surgically implante d into the body, automoti ve safety or security devices, life support products or other crit- ical applications. incl usion of cirrus products in such ap plications is understood to be full y at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or im plied, including the implied wa rranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er's customer uses or permits the use of ci rrus products in critical ap plications, customer agrees , by such use, to fully indemnify cirrus, its officers, directors, employees, distributo rs and other agents from any and all liability, including at- torneys' fees and costs, that may result fr om or arise in connect ion with these uses. cirrus logic, cirrus, the cirrus logic logo designs, exl core, and the exl core logo design are trademarks of cirrus logic, inc . all other brand and product names in this document may be trademarks or service marks of their respective owners. |
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